Implementing 1x2 DeMultiplexer

Duration: 5 min

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Module outline

  1. About Course: About the Course
  2. Paper-2 | Programming & Data Structures: C Fundamentals, Control Flow, Functions, Arrays & Pointers, Storage Classes, Structures & Enums, DMA, Macros, Scoping & File Handling, Introduction to DS, Array, Stack, Queue, Linked List, Tree, Graphs, Hashing
  3. Paper-2 | Databases / DBMS & SQL: Basics of DBMS, ER Diagram, Relational Model & Functional Dependencies, Keys & Integrity Constraints, Normalization (1NF - BCNF), Decomposition Properties & 4NF, File Organization & Indexing, Relational Algebra, SQL, Relational Calculus, Transaction Management, Concurrency Control
  4. Paper-2 | Algorithms: Algorithm Analysis, Time Complexity Analysis, Sorting Algorithms, Greedy Algorithms, Dynamic Programming, Minimum Spanning Trees, Shortest Path Algos
  5. Paper-2 | Computer Networks & Security: Introduction to CN, Data Communication, DLL: Access Control, DLL: Flow Control, DLL: Error Control, DLL: Framing, Data Link Layer - Ethernet, Net Layer: IPv4 & Proto, Net Layer: IP Addressing, Net Layer:Routing Protocol, Transport Layer Services, TL: Congestion & UDP, Application Layer, Hardware Basics, Network Access Technologies, Network Security
  6. Paper-2 | Digital Logic: Digital Systems & Boolean Basics, Logic Gates & Hardware, Boolean Expression, Boolean Minimization, Combinational Circuit, Sequential Circuits, Number System, Number Representation, Floating Point Rep
  7. Paper-2 | Operating System: Introduction to OS, Process Management, CPU Scheduling, Process Synchronization, Threads & Process Creation, Deadlock, Memory Management, Virtual Memory, Disc Scheduling, File Management
  8. Paper-2 | Theory of Computation: Introduction to TOC, Deterministic FA (DFA), Non-Deterministic FA, Regular Expressions, Grammar, Regular Language Properties, Moore & Mealy Machines, Pushdown Automata & CFG, Turing Machines
  9. Paper-2 | Computer Organization & Architecture: Basics of COA, Cache Memory Organization, Input Output Organisation, Pipelining, Instr Formats & Modes, Control Unit Design, Programming the Basic Computer
  10. Paper-2 | Compiler Design: Intro to Compilers, Lexical Analysis, Grammar & CFG, Syntax Analysis: Top-Down, Syntax Analysis: Bottom-Up, Semantic Analysis & SDT, Intermediate Code Gen, Code Optimization, Run Time Environment
  11. Paper-1 | General Awareness: Polity, Physics, Biology, Chemistry, Static General Knowledge, GK- Current Affairs, History, Geography, Indian Economy, Environment
  12. Paper-1 | Logical Reasoning: Series (Number and Letter Series) (Numerical Relations and Reasoning), Coding Decoding, Non Verbal Reasoning (Spatial Aptitude) (Spatial Reasoning) (Visual Reasoning), Data Interpretation, Blood Relations, Syllogisms, Deductive and Inductive Reasoning (Logical Deduction and Induction) (Prepositional Reasoning), Selection Decision Table (Decision Making), Clock, Calendar, Cubes & Dices, Directions (Direction Test), Analogy, Seating Arrangements, Analytical Reasoning (Counting Figures Reasoning)
  13. Paper-1 | Quantitative Aptitude: Ratio and Proportion (Ratios), Mixture and Alligation, Permutation and Combination, Number System, HCF LCM, Speed Time and Distance, Average, Age Problems, Percentage, Profit and Loss, Time and Work, Pipe and Cistern, Simple Interest and Compound Interest, Powers and Exponents (Surds and Indices), Mensuration and Geometry, Probability, Statistics, Arithmetic, Algebra
  14. Paper-1 | English: Vocabulary, Comprehension / Reading Comprehension / Unseen Passages (Critical Reasoning) (Paragraph Questions), Sentence Re-arrangements (Para Jumbles) (Narrative Sequencing), Sentence Correction (Error Correction), Sentence Completion (Fill in the blanks), Sentence Construction, Cloze Test (Cloze Passage)
  15. Coal India Previous Year Paper:
  16. Engineering Mathematics: Set Theory, Relations, Functions, Graph Theory, Group Theory, Propositional and Predicate Logic, Linear Algebra, Calculus
  17. Coal India Mock Test:
AI summary & chapters

AI Summary

An AI-generated summary of this video lecture.

This educational video provides a comprehensive tutorial on the 1-to-2 Demultiplexer, a fundamental digital logic component used in computer architecture. The instructor systematically breaks down the concept by first presenting the block diagram, then establishing the functional behavior through a truth table, and finally constructing the physical logic circuit using standard logic gates. The lecture emphasizes the relationship between the select line and the routing of the single data input to one of the two available outputs, providing a clear visual guide for students.

Chapters

  1. 0:00 – 2:00 00:00-02:00

    The session begins with the title "1 to 2 Demultiplexer" underlined at the top of the whiteboard. The instructor draws a square block diagram and writes "DeMux 1x2" inside it. He labels the single input line entering from the left as 'I', representing the data signal. On the right side of the block, he draws two output terminals labeled 'O0' and 'O1'. At the bottom of the block, he adds a control input line labeled 'S', which serves as the select line. He verbally explains that this device is designed to take a single input and distribute it to one of the two outputs depending on the logic level of the select line S. The "Knowledge Gate" logo is visible in the bottom right corner throughout the lecture.

  2. 2:00 – 4:34 02:00-04:34

    To define the logic, the instructor draws a truth table next to the block diagram. He sets up columns for the select line 'S' and the outputs 'O1' and 'O0'. He populates the table with binary values: in the first row where S is 0, he writes 'I' in the O0 column and '0' in the O1 column. In the second row where S is 1, he writes 'I' in the O1 column and '0' in the O0 column. Following this, he sketches the logic circuit diagram. He draws two AND gates. The top gate takes the input 'I' and the inverted select line (NOT S) to generate output 'O0'. The bottom gate takes input 'I' and the non-inverted select line 'S' to generate output 'O1'. He traces the lines to show how the select line controls which AND gate is enabled.

The video effectively demonstrates the design flow of a digital component from abstraction to implementation. By starting with the block diagram, the instructor establishes the interface. The truth table clarifies the functional requirements, showing that the input 'I' is routed to 'O0' when S=0 and to 'O1' when S=1. The final circuit diagram confirms this logic using two AND gates and an inverter, ensuring that only one output is active at any given time. This progression helps students understand how to translate a functional specification into a working logic circuit.

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