Decoder

Duration: 1 min

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Inside: a video lesson and guided study material.

Module outline

  1. Section A | English: Vocabulary, Comprehension / Reading Comprehension / Unseen Passages (Critical Reasoning) (Paragraph Questions), Preposition, Sentence Correction (Error Correction), Sentence Completion (Fill in the blanks), Articles, Sentence Re-arrangements (Para Jumbles) (Narrative Sequencing), Verbal Analogy (Word Based Analogy)
  2. Section A | Quant Aptitude: Ratio and Proportion (Ratios), Mixture and Alligation, Permutation and Combination, Number System, HCF LCM, Sequence and Series (Series), Speed Time and Distance, Arithmetic, Algebra, Powers and Exponents (Surds and Indices), Average, Age Problems, Percentage, Profit and Loss, Partnership, Time and Work, Simple Interest and Compound Interest, Mensuration and Geometry, Probability, Pipe and Cistern
  3. Section A | Reasoning: Series (Number and Letter Series) (Numerical Relations and Reasoning), Coding Decoding, Data Sufficiency, Calendar, Clock, Blood Relations, Directions (Direction Test), Seating Arrangements, Ranking, Order and Sequence, Puzzle Solving (Puzzles)
  4. Section B | C Programming: C Programming by Yash Sir, Coding Questions by Yash Sir
  5. Section B | Data Structures: Algorithm Analysis, Greedy Algorithms, Time Complexity Analysis, Sorting Algorithms, Introduction to DS, Array, Stack, Queue, Linked List, Tree, Graphs
  6. Section B | OOP (C++): Object Oriented Programming (OOPS), Programming in C++
  7. Section B | OS: Introduction to OS, Process Management, CPU Scheduling, Process Synchronization, Threads & Process Creation, Deadlock, Memory Management, Virtual Memory, Disc Scheduling, File Management, Windows OS
  8. Section B | Networking: Introduction to CN, Data Communication, DLL: Access Control, DLL: Flow Control, DLL: Error Control, DLL: Framing, Data Link Layer - Ethernet, Net Layer: IPv4 & Proto, Net Layer: IP Addressing, Net Layer:Routing Protocol, Transport Layer Services, TL: Congestion & UDP, Application Layer, Hardware basics
  9. Section B | AI & Big Data Basics: AI & ML by Arun Sir, Big Data Systems
  10. Section C | Digital Electronics: Digital Systems & Boolean Basics, Logic Gates & Hardware, Boolean Expression, Boolean Minimization, Combinational Circuit, Sequential Circuits, Number System, Number Representation, Analog-Digital Conversion
  11. Section A, C | Comp. Fundamentals, COA: Basics of COA, Floating Point Rep, Cache Memory Organization, Input Output Organisation, Pipelining, Instr Formats & Modes, Control Unit Design, Register Transfer and Microoperations, Multiprocessors, Programming the Basic Computer
  12. MOCK TEST:
AI summary & chapters

AI Summary

An AI-generated summary of this video lecture.

The video presents a digital logic design problem: constructing a 7-to-128 decoder using 3-to-8 decoders. The instructor writes the question "Q 7-to-128 from 3-to-8?" in orange text. He then uses red marker to draw a hierarchical tree structure on the whiteboard to solve it. The diagram consists of boxes representing the decoders, arranged in levels. He circles numbers like 16 and 128 to denote the number of blocks and total outputs. He performs a calculation "1 + 2 + 16" to determine the total count of decoders required, circling the final answer "19". He also writes "16 x 8" to verify the output capacity.

Chapters

  1. 0:00 – 1:09 00:00-01:09

    The video covers the entire derivation process. Initially, the question is displayed. The instructor draws a vertical tree of boxes. He writes "16" and "128" near the bottom, indicating the leaf nodes. He writes "1 + 2 + 16" on the left side. He circles "19" as the sum. He writes "16 x 8" and circles "128" to show the multiplication. He also writes "8" at the bottom. The drawing shows a top box, a middle section, and a bottom section of boxes. He also circles a number "65" which appears to be a draft or intermediate value before settling on the final calculation.

The instructor demonstrates a systematic method for expanding decoder capabilities. By organizing the 3-to-8 decoders into three levels (1 top, 2 middle, 16 bottom), he ensures all 7 input lines are utilized to select the correct output among 128 possibilities. The calculation confirms that 19 individual 3-to-8 decoders are necessary to build the larger 7-to-128 unit. This hierarchical approach allows for modular design of complex digital circuits.

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