Practice Question (Gate 1990)

Duration: 2 min

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Inside: a video lesson and guided study material.

Module outline

  1. Section A | English: Vocabulary, Comprehension / Reading Comprehension / Unseen Passages (Critical Reasoning) (Paragraph Questions), Preposition, Sentence Correction (Error Correction), Sentence Completion (Fill in the blanks), Articles, Sentence Re-arrangements (Para Jumbles) (Narrative Sequencing), Verbal Analogy (Word Based Analogy)
  2. Section A | Quant Aptitude: Ratio and Proportion (Ratios), Mixture and Alligation, Permutation and Combination, Number System, HCF LCM, Sequence and Series (Series), Speed Time and Distance, Arithmetic, Algebra, Powers and Exponents (Surds and Indices), Average, Age Problems, Percentage, Profit and Loss, Partnership, Time and Work, Simple Interest and Compound Interest, Mensuration and Geometry, Probability, Pipe and Cistern
  3. Section A | Reasoning: Series (Number and Letter Series) (Numerical Relations and Reasoning), Coding Decoding, Data Sufficiency, Calendar, Clock, Blood Relations, Directions (Direction Test), Seating Arrangements, Ranking, Order and Sequence, Puzzle Solving (Puzzles)
  4. Section B | C Programming: C Programming by Yash Sir, Coding Questions by Yash Sir
  5. Section B | Data Structures: Algorithm Analysis, Greedy Algorithms, Time Complexity Analysis, Sorting Algorithms, Introduction to DS, Array, Stack, Queue, Linked List, Tree, Graphs
  6. Section B | OOP (C++): Object Oriented Programming (OOPS), Programming in C++
  7. Section B | OS: Introduction to OS, Process Management, CPU Scheduling, Process Synchronization, Threads & Process Creation, Deadlock, Memory Management, Virtual Memory, Disc Scheduling, File Management, Windows OS
  8. Section B | Networking: Introduction to CN, Data Communication, DLL: Access Control, DLL: Flow Control, DLL: Error Control, DLL: Framing, Data Link Layer - Ethernet, Net Layer: IPv4 & Proto, Net Layer: IP Addressing, Net Layer:Routing Protocol, Transport Layer Services, TL: Congestion & UDP, Application Layer, Hardware basics
  9. Section B | AI & Big Data Basics: AI & ML by Arun Sir, Big Data Systems
  10. Section C | Digital Electronics: Digital Systems & Boolean Basics, Logic Gates & Hardware, Boolean Expression, Boolean Minimization, Combinational Circuit, Sequential Circuits, Number System, Number Representation, Analog-Digital Conversion
  11. Section A, C | Comp. Fundamentals, COA: Basics of COA, Floating Point Rep, Cache Memory Organization, Input Output Organisation, Pipelining, Instr Formats & Modes, Control Unit Design, Register Transfer and Microoperations, Multiprocessors, Programming the Basic Computer
  12. MOCK TEST:
AI summary & chapters

AI Summary

An AI-generated summary of this video lecture.

The video presents an educational lecture on computer architecture, specifically solving a cache memory addressing problem from a 1990 Gate exam. The instructor analyzes a block-set associative cache system with 128 blocks divided into four sets, a main memory of 16,384 blocks, and a block size of 256 eight-bit words. The lecture addresses two key questions: determining the total bits required for main memory addressing and calculating the bit distribution for the Tag, Set, and Word fields. The instructor uses a diagram to visually break down the physical address into its constituent parts.

Chapters

  1. 0:00 – 1:47 00:00-01:47

    The video opens with a static slide displaying a computer architecture problem. The text reads: 'A block-set associative cache memory consists of 128 blocks divided into four block sets. The main memory consists of 16,384 blocks and each block contains 256 eight-bit words.' The instructor reads these parameters aloud, highlighting the cache size, set count, main memory capacity, and block size. He identifies the two questions to be answered: total address bits and field breakdown.

The lecture demonstrates a step-by-step approach to solving cache addressing problems. It starts with parsing the problem parameters, then calculates the physical address width, and finally decomposes this address into the specific fields required for cache lookup (Tag, Set, Offset). The visual aid of the diagram helps in understanding how the address bits are partitioned between the main memory and the cache components.

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