Practice Question

Duration: 2 min

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Module outline

  1. Section A | English: Vocabulary, Comprehension / Reading Comprehension / Unseen Passages (Critical Reasoning) (Paragraph Questions), Preposition, Sentence Correction (Error Correction), Sentence Completion (Fill in the blanks), Articles, Sentence Re-arrangements (Para Jumbles) (Narrative Sequencing), Verbal Analogy (Word Based Analogy)
  2. Section A | Quant Aptitude: Ratio and Proportion (Ratios), Mixture and Alligation, Permutation and Combination, Number System, HCF LCM, Sequence and Series (Series), Speed Time and Distance, Arithmetic, Algebra, Powers and Exponents (Surds and Indices), Average, Age Problems, Percentage, Profit and Loss, Partnership, Time and Work, Simple Interest and Compound Interest, Mensuration and Geometry, Probability, Pipe and Cistern
  3. Section A | Reasoning: Series (Number and Letter Series) (Numerical Relations and Reasoning), Coding Decoding, Data Sufficiency, Calendar, Clock, Blood Relations, Directions (Direction Test), Seating Arrangements, Ranking, Order and Sequence, Puzzle Solving (Puzzles)
  4. Section B | C Programming: C Programming by Yash Sir, Coding Questions by Yash Sir
  5. Section B | Data Structures: Algorithm Analysis, Greedy Algorithms, Time Complexity Analysis, Sorting Algorithms, Introduction to DS, Array, Stack, Queue, Linked List, Tree, Graphs
  6. Section B | OOP (C++): Object Oriented Programming (OOPS), Programming in C++
  7. Section B | OS: Introduction to OS, Process Management, CPU Scheduling, Process Synchronization, Threads & Process Creation, Deadlock, Memory Management, Virtual Memory, Disc Scheduling, File Management, Windows OS
  8. Section B | Networking: Introduction to CN, Data Communication, DLL: Access Control, DLL: Flow Control, DLL: Error Control, DLL: Framing, Data Link Layer - Ethernet, Net Layer: IPv4 & Proto, Net Layer: IP Addressing, Net Layer:Routing Protocol, Transport Layer Services, TL: Congestion & UDP, Application Layer, Hardware basics
  9. Section B | AI & Big Data Basics: AI & ML by Arun Sir, Big Data Systems
  10. Section C | Digital Electronics: Digital Systems & Boolean Basics, Logic Gates & Hardware, Boolean Expression, Boolean Minimization, Combinational Circuit, Sequential Circuits, Number System, Number Representation, Analog-Digital Conversion
  11. Section A, C | Comp. Fundamentals, COA: Basics of COA, Floating Point Rep, Cache Memory Organization, Input Output Organisation, Pipelining, Instr Formats & Modes, Control Unit Design, Register Transfer and Microoperations, Multiprocessors, Programming the Basic Computer
  12. MOCK TEST:
AI summary & chapters

AI Summary

An AI-generated summary of this video lecture.

The video presents a worked example for calculating Effective Memory Access Time (EMAT) in a computer architecture context. The problem specifies a cache hit rate of 80%, cache access time of 5ns, and main memory access time of 100ns. The instructor calculates EMAT for both hierarchical and simultaneous access methods.

Chapters

  1. 0:00 – 2:00 00:00-02:00

    The video begins with a clear problem statement displayed at the top of the screen: 'Calculate the EMAT for a machine with a cache hit rate of 80% where cache access time is 5ns and main memory access time is 100ns, both for simultaneous and hierarchical access.' The instructor systematically underlines critical values on the text, specifically 'EMAT', '80%', '5ns', and '100ns', to emphasize the variables needed for the formula. He then proceeds to write out the calculation for hierarchical access first. He writes the equation 0.8[5ns] + 0.2[5ns + 100ns], representing the hit rate multiplied by cache time plus the miss rate multiplied by the sum of cache and memory times. He calculates the first term as 4ns and the second term as 21ns, summing them to get 25ns. He draws a horizontal line to separate this from the next part and begins writing the formula for simultaneous access, starting with 0.8[5ns] + 0.2[.

  2. 2:00 – 2:16 02:00-02:16

    Continuing from the previous step, the instructor completes the formula for simultaneous access. He writes the full expression 0.8[5ns] + 0.2[100ns] on the board. He performs the multiplication to get 4ns and 20ns. He adds these values together to find the final EMAT for simultaneous access, which is 24ns. He clearly underlines the final result 24ns to signify the completion of the problem. The video ends with this final answer visible on the screen alongside the previous calculation.

This lecture segment effectively contrasts two methods of calculating Effective Memory Access Time (EMAT) based on system architecture. The instructor first tackles the hierarchical access model, where a cache miss requires accessing the cache first and then the main memory, leading to a total miss penalty of 5ns + 100ns. This results in an EMAT of 25ns. He then shifts to the simultaneous access model, where the cache and main memory are accessed in parallel. In this scenario, a miss simply incurs the main memory access time of 100ns as the penalty, without the initial cache delay. This yields a slightly faster EMAT of 24ns overall.

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