Race condition Example
Duration: 4 min
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Module outline
- Section A | English: Vocabulary, Comprehension / Reading Comprehension / Unseen Passages (Critical Reasoning) (Paragraph Questions), Preposition, Sentence Correction (Error Correction), Sentence Completion (Fill in the blanks), Articles, Sentence Re-arrangements (Para Jumbles) (Narrative Sequencing), Verbal Analogy (Word Based Analogy)
- Section A | Quant Aptitude: Ratio and Proportion (Ratios), Mixture and Alligation, Permutation and Combination, Number System, HCF LCM, Sequence and Series (Series), Speed Time and Distance, Arithmetic, Algebra, Powers and Exponents (Surds and Indices), Average, Age Problems, Percentage, Profit and Loss, Partnership, Time and Work, Simple Interest and Compound Interest, Mensuration and Geometry, Probability, Pipe and Cistern
- Section A | Reasoning: Series (Number and Letter Series) (Numerical Relations and Reasoning), Coding Decoding, Data Sufficiency, Calendar, Clock, Blood Relations, Directions (Direction Test), Seating Arrangements, Ranking, Order and Sequence, Puzzle Solving (Puzzles)
- Section B | C Programming: C Programming by Yash Sir, Coding Questions by Yash Sir
- Section B | Data Structures: Algorithm Analysis, Greedy Algorithms, Time Complexity Analysis, Sorting Algorithms, Introduction to DS, Array, Stack, Queue, Linked List, Tree, Graphs
- Section B | OOP (C++): Object Oriented Programming (OOPS), Programming in C++
- Section B | OS: Introduction to OS, Process Management, CPU Scheduling, Process Synchronization, Threads & Process Creation, Deadlock, Memory Management, Virtual Memory, Disc Scheduling, File Management, Windows OS
- Section B | Networking: Introduction to CN, Data Communication, DLL: Access Control, DLL: Flow Control, DLL: Error Control, DLL: Framing, Data Link Layer - Ethernet, Net Layer: IPv4 & Proto, Net Layer: IP Addressing, Net Layer:Routing Protocol, Transport Layer Services, TL: Congestion & UDP, Application Layer, Hardware basics
- Section B | AI & Big Data Basics: AI & ML by Arun Sir, Big Data Systems
- Section C | Digital Electronics: Digital Systems & Boolean Basics, Logic Gates & Hardware, Boolean Expression, Boolean Minimization, Combinational Circuit, Sequential Circuits, Number System, Number Representation, Analog-Digital Conversion
- Section A, C | Comp. Fundamentals, COA: Basics of COA, Floating Point Rep, Cache Memory Organization, Input Output Organisation, Pipelining, Instr Formats & Modes, Control Unit Design, Register Transfer and Microoperations, Multiprocessors, Programming the Basic Computer
- MOCK TEST:
AI summary & chapters
AI Summary
An AI-generated summary of this video lecture.
This video solves a GATE-2015 operating-systems concurrency question. Two functions, P1 and P2, share a variable B with initial value 2. P1 executes C = B - 1; then B = 2 * C;, while P2 executes D = 2 * B; then B = D - 1;. The question asks for the number of distinct values that B can possibly take after execution. The instructor labels the four instructions I11, I12 for P1 and I21, I22 for P2. Because each function's two instructions must preserve their internal order, the possible interleavings are the six permutations of choosing which P1 instruction and which P2 instruction occur at each step. A table with Case 1 through Case 6 lists the six interleavings of I11, I12, I21, and I22. The instructor evaluates each case by tracking the shared variable B (and local variables C and D) through the sequence. For example, one interleaving gives I11: C = 2 - 1 = 1; then I21: D = 2 * 2 = 4; then I12: B = 2 * 1 = 2; then I22: B = 4 - 1 = 3. Other interleavings yield final values such as 2 and 3 (and in some orderings, other intermediate results). By circling the final B values across all six cases and removing duplicates, the instructor concludes that B can take 3 distinct final values. The answer '3' is circled at the bottom of the question slide.
Chapters
0:00 – 2:00 00:00-02:00
The slide presents the GATE-2015 question in an orange-and-white two-column table labeled P1() and P2(). The top line states that the two functions share a variable B with an initial value of 2 and execute concurrently. P1 contains 'C = B - 1;' then 'B = 2 * C;'; P2 contains 'D = 2 * B;' then 'B = D - 1;'. The red bottom line asks for the number of distinct values B can possibly take after execution. Handwritten blue annotations progressively label the P1 steps as I1, J1 and the P2 steps as I2, J2 (later refined to I11, I12 and I21, I22), establishing the instruction labels used for interleaving analysis.
2:00 – 3:58 02:00-03:58
The slide now shows two code blocks headed P1() and P2() with labeled instructions (I11) C = B - 1;, (I12) B = 2 * C; and (I21) D = 2 * B;, (I22) B = D - 1;. Below, a green-headed table lists six columns Case1 through Case6, each containing a vertical sequence of the four instruction labels in different orders. Blue vertical line marks highlight selected rows in Case1-Case4 as the instructor computes each interleaving. On-screen values such as C=1, D=4, B=2 appear during the step-by-step evaluation. The instructor circles key intermediate values (e.g., B=3) and crosses out redundant steps, then returns to the original question slide where the final answer '3' is circled at the bottom, indicating three distinct possible values for B.
The core teaching point is systematic enumeration of legal interleavings in a concurrent execution where each process's internal instruction order must be preserved. With two instructions per process, there are C(4,2) = 6 valid interleavings, which the instructor tabulates as Case1-Case6. The method is: (1) label each instruction, (2) list all order-preserving interleavings, (3) simulate the shared variable B through each sequence while tracking local variables C and D, (4) collect the final B values and count distinct ones. The worked example shows how one interleaving produces C=1, D=4, and a final B=3, while others produce different finals. The conclusion is that the number of distinct values B can take is 3, which is circled as the answer. This case-by-case table method is the key exam technique for GATE concurrency questions of this type.