Set Associative Mapping Part-2

Duration: 4 min

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Module outline

  1. About the Course: About the Course
  2. Section 1 | Language (Hindi): भाषा, लिपि, ध्वनि, वर्ण, अक्षर, स्वर, व्यंजन, मात्रा और संयुक्ताक्षर, वर्तनी, वर्ण-विन्यास, अनुस्वार, अनुनासिक, चंद्रबिंदु और ‘र’ के रूप, शब्द, पद और शब्द-भेद, संज्ञा और सर्वनाम, विशेषण और क्रिया, लिंग, वचन, पुरुष और कारक, काल, वाच्य, वाक्य और वाक्य-भेद, संधि, समास, विलोम शब्द, पर्यायवाची शब्द, सामान्य अशुद्धियाँ, अनेक शब्दों के लिए एक शब्द, मुहावरे और लोकोक्तियाँ, अपठित गद्यांश और अपठित पद्यांश, Multi-Topic Content (Cross-Concept Material), वर्णमाला
  3. Section 1 | Language (उर्दू भाषा — 22 प्रश्न (निश्चित)): Spelling & Diacritics, Grammar (اسم, فعل, صفت, ضمیر), Vocabulary, Idioms & Proverbs, Comprehension
  4. Section 1 | Language (বাংলা / बांग्ला भाषा — 22 प्रश्न (निश्चित)): Bangla Script and Sounds, Bangla Grammar and Usage, Bangla Word Formation and Vocabulary, Reading and Text Interpretation
  5. Section 1 | Language (English): Vocabulary, Noun, Subject Verb Agreement (Verb Noun Agreement), Adjectives, Tenses, Pronoun, Verb, Adverb, Preposition, Articles, Determiner, Conjunction, Modals, Active Passive Voice (Voice), Direct and Indirect Speech, Sentence Correction (Error Correction), Sentence Completion (Fill in the blanks), Sentence Construction, Sentence Re-arrangements (Para Jumbles) (Narrative Sequencing), Comprehension / Reading Comprehension / Unseen Passages (Critical Reasoning) (Paragraph Questions), Cloze Test (Cloze Passage), Verbal Analogy (Word Based Analogy), Facts, Inference and Judgements
  6. Section 2 | Primary Maths & Reasoning: Ratio and Proportion (Ratios), Divisibility Rules, Mixture and Alligation, Permutation and Combination, Number System, HCF LCM, Sequence and Series (Series), Speed Time and Distance, Series (Number and Letter Series) (Numerical Relations and Reasoning), Coding Decoding, Non Verbal Reasoning (Spatial Aptitude) (Spatial Reasoning) (Visual Reasoning), Percentage, Average, Profit and Loss, Simple Interest and Compound Interest, Time and Work, Mensuration and Geometry, Age Problems, Arithmetic, Powers and Exponents (Surds and Indices), Algebra, Probability, Trigonometry, Syllogisms, Seating Arrangements, Blood Relations, Directions (Direction Test), Analytical Reasoning (Counting Figures Reasoning), Puzzle Solving (Puzzles), Calendar, Clock, Cubes & Dices, Venn Diagram, Data Arrangement, Inequality, Analogy, Ranking, Order and Sequence
  7. Section 2 | General Awareness (GK + Current Affairs): Polity, Physics, Biology, State Wise GK, Chemistry, History, Geography, Indian Economy, Environment, GK- Current Affairs, Static General Knowledge
  8. Section 3 | Computer System and Org. (CSO): Basics of COA, Floating Point Rep, Cache Memory Organization, Instr Formats & Modes, Programming the Basic Computer, Input Output Organisation, Register Transfer and Microoperations, Control Unit Design
  9. Section 3 | Database Management System: Basics of DBMS, ER Diagram, Relational Model & Functional Dependencies, Keys & Integrity Constraints, Normalization (1NF - BCNF), Decomposition Properties & 4NF, SQL, File Organization & Indexing, Relational Algebra, Relational Calculus, Transaction Management, Concurrency Control
  10. Section 3 | Operating System: Introduction to OS, Process Management, CPU Scheduling, Threads & Process Creation, Memory Management, Virtual Memory, Disc Scheduling, File Management, Process Synchronization
  11. Section 3 | Computer Networks: Introduction to CN, Data Communication, DLL: Access Control, DLL: Flow Control, DLL: Error Control, Data Link Layer - Ethernet, Net Layer: IPv4 & Proto, Net Layer: IP Addressing, Transport Layer Services, TL: Congestion & UDP, Application Layer, Hardware basics
  12. Section 3 | Data Structures: Introduction to DS, Array, Stack, Queue, Linked List, Tree, Graphs, Hashing, Algorithm Analysis, Time Complexity Analysis, Sorting Algorithms, Greedy Algorithms, Minimum Spanning Trees, Shortest Path Algos
  13. Section 3 | Theory Of Computation & Compiler Design: Introduction to TOC, Deterministic FA (DFA), Non-Deterministic FA, Regular Expressions, Grammar, Regular Language Properties, Moore & Mealy Machines, Pushdown Automata & CFG, Turing Machines, Intro to Compilers, Lexical Analysis, Grammar & CFG, Syntax Analysis: Top-Down, Syntax Analysis: Bottom-Up, Semantic Analysis & SDT, Intermediate Code Gen, Code Optimization
  14. Section 3 | Emerging Trends (AI, Societal Ethics & MS Office): Artificial Intelligence, Emerging Tech Trends, Society, Law & Ethics, MS Office Applications
  15. Section 3 | Software Engineering: Fundamentals of Software Engineering, Software Requirements and Quality Assurance, Software Design, Estimation and Metrics, Software Maintenance and Configuration Management, Software Testing
  16. Section 3 | C Programming: C Fundamentals, Control Flow, Functions, Arrays & Pointers, Storage Classes, Structures & Enums, DMA, Macros, Scoping & File Handling
  17. Section 3 | OOPS, C++, JAVA, HTML: OOPS with C++, Java, HTML Basics, CSS
  18. Section 3 | Java: Java Fundamentals, Array, String, IO & References
  19. Section 3 | Python: Introduction to Python, Tokens, Variables, Data Types, I/O, Operators & Expressions, Control Flow & Looping, Collections & Strings, Functions & Modules, File Handling & Data Analysis
  20. Section 3 | Digital Electronics: Digital Systems & Boolean Basics, Logic Gates & Hardware, Boolean Expression, Boolean Minimization, Combinational Circuit, Sequential Circuits, Number System, Number Representation
  21. Section 3 | Multimedia: Multimedia
  22. BPSC Previous Year Papers:
  23. BPSC Full Mock Tests:
AI summary & chapters

AI Summary

An AI-generated summary of this video lecture.

The video lecture focuses on set-associative cache mapping in computer architecture. The instructor begins by defining the structure of physical addresses and cache lines, specifically breaking down the address into Tag, Set, and Block Offset fields. He uses diagrams to illustrate how main memory blocks are mapped to cache sets. The lecture progresses to a concrete example involving a 2-way set-associative cache with 4 cache lines (2 sets) and 16 main memory blocks. Finally, the hardware implementation of this mapping is explained using a block diagram showing multiplexers, comparators, and the selection logic.

Chapters

  1. 0:00 – 2:00 00:00-02:00

    The instructor introduces the formula for the number of sets and breaks down the physical address structure. He displays a diagram where the 'Main Memory (Physical Address)' is split into 'Block Number' and 'Block Offset'. He annotates the diagram with bit counts, writing '8' for the Block Number and '2' for the Block Offset. He then transitions to the cache structure, showing 'Tag', 'Set', and 'Block Offset'. He writes '2' for Tag bits and '2' for Cache Line (Set) bits in one example, and later '3' for Tag and '1' for Set in another, illustrating how address bits are allocated. He writes 'Bits Transferred' with values like '2w', '4w', '3w', '8w', likely referring to word sizes or data transfer widths associated with the cache lines. He circles 'Set 1' in the lower diagram to emphasize the set selection process.

  2. 2:00 – 4:17 02:00-04:17

    The lecture moves to a specific mapping example. A diagram shows a cache with 'Set Number-0' (containing CL-0, CL-1) and 'Set Number-1' (containing CL-2, CL-3) connected to main memory blocks B-0 through B-15. The instructor writes a binary address '1001 01' at the top. He draws lines connecting specific cache lines to memory blocks, highlighting B-8 and B-9. A detailed table is shown mapping Set Numbers to Cache Lines (CL-0 to CL-3) and listing the specific Blocks (B-0, B-2, etc.) and Words (W-0, W-1, etc.) stored in each. The instructor then presents a 'Hardware Architecture' diagram for 2-Way Set Associative Mapping. This diagram illustrates the flow from Tag, Set Number, and Block Offset inputs through Multiplexers to select a set, then through Comparators to check the Tag, and finally through an OR gate to produce the result. He highlights 'Set-1 (Selected)' in the cache memory block to demonstrate the selection mechanism.

The video provides a comprehensive overview of set-associative cache mapping, starting from theoretical address breakdown to practical hardware implementation. The instructor effectively uses diagrams to visualize the relationship between main memory blocks and cache sets, demonstrating how address bits are partitioned into Tag, Set, and Offset. The transition from abstract formulas to a concrete 2-way set-associative example with 16 memory blocks helps clarify the mapping process. The final hardware architecture diagram ties the concepts together by showing the physical components like multiplexers and comparators required to execute the mapping logic, ensuring students understand both the logical structure and the physical realization of cache memory systems.

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