Memory Extension

Duration: 6 min

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Inside: a video lesson and guided study material.

Module outline

  1. About the Course: About the Course
  2. Section 1 | Language (Hindi): भाषा, लिपि, ध्वनि, वर्ण, अक्षर, स्वर, व्यंजन, मात्रा और संयुक्ताक्षर, वर्तनी, वर्ण-विन्यास, अनुस्वार, अनुनासिक, चंद्रबिंदु और ‘र’ के रूप, शब्द, पद और शब्द-भेद, संज्ञा और सर्वनाम, विशेषण और क्रिया, लिंग, वचन, पुरुष और कारक, काल, वाच्य, वाक्य और वाक्य-भेद, संधि, समास, विलोम शब्द, पर्यायवाची शब्द, सामान्य अशुद्धियाँ, अनेक शब्दों के लिए एक शब्द, मुहावरे और लोकोक्तियाँ, अपठित गद्यांश और अपठित पद्यांश, Multi-Topic Content (Cross-Concept Material), वर्णमाला
  3. Section 1 | Language (उर्दू भाषा — 22 प्रश्न (निश्चित)): Spelling & Diacritics, Grammar (اسم, فعل, صفت, ضمیر), Vocabulary, Idioms & Proverbs, Comprehension
  4. Section 1 | Language (বাংলা / बांग्ला भाषा — 22 प्रश्न (निश्चित)): Bangla Script and Sounds, Bangla Grammar and Usage, Bangla Word Formation and Vocabulary, Reading and Text Interpretation
  5. Section 1 | Language (English): Vocabulary, Noun, Subject Verb Agreement (Verb Noun Agreement), Adjectives, Tenses, Pronoun, Verb, Adverb, Preposition, Articles, Determiner, Conjunction, Modals, Active Passive Voice (Voice), Direct and Indirect Speech, Sentence Correction (Error Correction), Sentence Completion (Fill in the blanks), Sentence Construction, Sentence Re-arrangements (Para Jumbles) (Narrative Sequencing), Comprehension / Reading Comprehension / Unseen Passages (Critical Reasoning) (Paragraph Questions), Cloze Test (Cloze Passage), Verbal Analogy (Word Based Analogy), Facts, Inference and Judgements
  6. Section 2 | Primary Maths & Reasoning: Ratio and Proportion (Ratios), Divisibility Rules, Mixture and Alligation, Permutation and Combination, Number System, HCF LCM, Sequence and Series (Series), Speed Time and Distance, Series (Number and Letter Series) (Numerical Relations and Reasoning), Coding Decoding, Non Verbal Reasoning (Spatial Aptitude) (Spatial Reasoning) (Visual Reasoning), Percentage, Average, Profit and Loss, Simple Interest and Compound Interest, Time and Work, Mensuration and Geometry, Age Problems, Arithmetic, Powers and Exponents (Surds and Indices), Algebra, Probability, Trigonometry, Syllogisms, Seating Arrangements, Blood Relations, Directions (Direction Test), Analytical Reasoning (Counting Figures Reasoning), Puzzle Solving (Puzzles), Calendar, Clock, Cubes & Dices, Venn Diagram, Data Arrangement, Inequality, Analogy, Ranking, Order and Sequence
  7. Section 2 | General Awareness (GK + Current Affairs): Polity, Physics, Biology, State Wise GK, Chemistry, History, Geography, Indian Economy, Environment, GK- Current Affairs, Static General Knowledge
  8. Section 3 | Computer System and Org. (CSO): Basics of COA, Floating Point Rep, Cache Memory Organization, Instr Formats & Modes, Programming the Basic Computer, Input Output Organisation, Register Transfer and Microoperations, Control Unit Design
  9. Section 3 | Database Management System: Basics of DBMS, ER Diagram, Relational Model & Functional Dependencies, Keys & Integrity Constraints, Normalization (1NF - BCNF), Decomposition Properties & 4NF, SQL, File Organization & Indexing, Relational Algebra, Relational Calculus, Transaction Management, Concurrency Control
  10. Section 3 | Operating System: Introduction to OS, Process Management, CPU Scheduling, Threads & Process Creation, Memory Management, Virtual Memory, Disc Scheduling, File Management, Process Synchronization
  11. Section 3 | Computer Networks: Introduction to CN, Data Communication, DLL: Access Control, DLL: Flow Control, DLL: Error Control, Data Link Layer - Ethernet, Net Layer: IPv4 & Proto, Net Layer: IP Addressing, Transport Layer Services, TL: Congestion & UDP, Application Layer, Hardware basics
  12. Section 3 | Data Structures: Introduction to DS, Array, Stack, Queue, Linked List, Tree, Graphs, Hashing, Algorithm Analysis, Time Complexity Analysis, Sorting Algorithms, Greedy Algorithms, Minimum Spanning Trees, Shortest Path Algos
  13. Section 3 | Theory Of Computation & Compiler Design: Introduction to TOC, Deterministic FA (DFA), Non-Deterministic FA, Regular Expressions, Grammar, Regular Language Properties, Moore & Mealy Machines, Pushdown Automata & CFG, Turing Machines, Intro to Compilers, Lexical Analysis, Grammar & CFG, Syntax Analysis: Top-Down, Syntax Analysis: Bottom-Up, Semantic Analysis & SDT, Intermediate Code Gen, Code Optimization
  14. Section 3 | Emerging Trends (AI, Societal Ethics & MS Office): Artificial Intelligence, Emerging Tech Trends, Society, Law & Ethics, MS Office Applications
  15. Section 3 | Software Engineering: Fundamentals of Software Engineering, Software Requirements and Quality Assurance, Software Design, Estimation and Metrics, Software Maintenance and Configuration Management, Software Testing
  16. Section 3 | C Programming: C Fundamentals, Control Flow, Functions, Arrays & Pointers, Storage Classes, Structures & Enums, DMA, Macros, Scoping & File Handling
  17. Section 3 | OOPS, C++, JAVA, HTML: OOPS with C++, Java, HTML Basics, CSS
  18. Section 3 | Java: Java Fundamentals, Array, String, IO & References
  19. Section 3 | Python: Introduction to Python, Tokens, Variables, Data Types, I/O, Operators & Expressions, Control Flow & Looping, Collections & Strings, Functions & Modules, File Handling & Data Analysis
  20. Section 3 | Digital Electronics: Digital Systems & Boolean Basics, Logic Gates & Hardware, Boolean Expression, Boolean Minimization, Combinational Circuit, Sequential Circuits, Number System, Number Representation
  21. Section 3 | Multimedia: Multimedia
  22. BPSC Previous Year Papers:
  23. BPSC Full Mock Tests:
AI summary & chapters

AI Summary

An AI-generated summary of this video lecture.

The video presents a detailed lecture on memory mapping and address decoding in computer architecture. The instructor, Sanchit Jain, uses a circuit diagram to explain how a CPU interfaces with multiple memory chips (RAM and ROM). The diagram features a CPU block connected to a 3-to-8 decoder and five memory chips: four RAM chips (labeled 128 x 8) and one ROM chip (labeled 128 x 8). The lecture focuses on determining the address range for each memory chip based on the connections to the decoder and the address bus lines. The instructor demonstrates how to calculate the hexadecimal addresses by analyzing the logic levels of the high-order address bits that control the chip select lines. He also clarifies the role of the lower address lines in accessing specific memory locations within a selected chip.

Chapters

  1. 0:00 – 2:00 00:00-02:00

    The instructor introduces the memory connection diagram, pointing out the CPU, address bus, and data bus. He identifies the specific memory components: four "128 x 8 RAM" blocks and one "128 x 8 ROM" block. He explains the function of the "Decoder" block, noting that it receives inputs from the upper address lines (16-11) to generate chip select signals (CS1, CS2, etc.). He also points out the "RD" (Read) and "WR" (Write) control lines that are connected to all memory chips, indicating that these signals control the direction of data flow. The visual evidence includes the clear labeling of "Address bus", "Decoder", and the memory blocks, along with the instructor's gestures indicating the flow of signals from the CPU to the memory chips. He establishes the context that the decoder is responsible for selecting which memory chip is active at any given time, while the RD/WR lines control the operation.

  2. 2:00 – 5:00 02:00-05:00

    The instructor begins the practical calculation of address ranges. He focuses on the ROM chip at the bottom of the diagram. He writes "10 -> 0 ROM" and "0 -> 1 RAM" on the screen, indicating that address bit 10 determines whether the ROM or RAM is selected. He circles the address lines AD9, AD8, and AD7, writing the numbers "7" and "8" to highlight their significance in the address calculation. He draws a vertical block diagram representing the memory space, labeling it "1024" and "10", likely referring to the total addressable space or specific bit positions. This section is critical for understanding how to derive the specific hexadecimal address range for each chip based on the decoder inputs and chip select logic. He explains that the "128 x 8" notation means the chip has 128 locations, each storing 8 bits of data.

  3. 5:00 – 5:36 05:00-05:36

    The instructor concludes the explanation by clarifying the role of the lower address lines. He points to the "AD7" line which is common to all chips, explaining that these lines (AD0-AD7) are used for internal addressing within the 128-byte memory chips. He emphasizes that while the decoder selects the chip, the lower bits select the specific byte within that chip. The visual evidence includes his hand gestures pointing to the "AD7" label and the "Data" bus connection. He reinforces the concept that the total address is a combination of the chip select bits (from the decoder) and the internal offset bits.

The lecture effectively bridges the gap between theoretical memory concepts and practical circuit implementation. By analyzing the specific connections in the diagram, the instructor demonstrates how to calculate address ranges for memory chips. The use of the decoder to map high-order address bits to chip select lines is a fundamental concept in memory organization. The instructor's step-by-step calculation, including the writing of logic levels and address bits, provides a clear method for students to solve similar problems. The distinction between chip selection and internal addressing is crucial for understanding how the CPU accesses specific data in a memory system.

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