SRAM DRAM

Duration: 7 min

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Module outline

  1. About the Course: About the Course
  2. Section 1 | Language (Hindi): भाषा, लिपि, ध्वनि, वर्ण, अक्षर, स्वर, व्यंजन, मात्रा और संयुक्ताक्षर, वर्तनी, वर्ण-विन्यास, अनुस्वार, अनुनासिक, चंद्रबिंदु और ‘र’ के रूप, शब्द, पद और शब्द-भेद, संज्ञा और सर्वनाम, विशेषण और क्रिया, लिंग, वचन, पुरुष और कारक, काल, वाच्य, वाक्य और वाक्य-भेद, संधि, समास, विलोम शब्द, पर्यायवाची शब्द, सामान्य अशुद्धियाँ, अनेक शब्दों के लिए एक शब्द, मुहावरे और लोकोक्तियाँ, अपठित गद्यांश और अपठित पद्यांश, Multi-Topic Content (Cross-Concept Material), वर्णमाला
  3. Section 1 | Language (उर्दू भाषा — 22 प्रश्न (निश्चित)): Spelling & Diacritics, Grammar (اسم, فعل, صفت, ضمیر), Vocabulary, Idioms & Proverbs, Comprehension
  4. Section 1 | Language (বাংলা / बांग्ला भाषा — 22 प्रश्न (निश्चित)): Bangla Script and Sounds, Bangla Grammar and Usage, Bangla Word Formation and Vocabulary, Reading and Text Interpretation
  5. Section 1 | Language (English): Vocabulary, Noun, Subject Verb Agreement (Verb Noun Agreement), Adjectives, Tenses, Pronoun, Verb, Adverb, Preposition, Articles, Determiner, Conjunction, Modals, Active Passive Voice (Voice), Direct and Indirect Speech, Sentence Correction (Error Correction), Sentence Completion (Fill in the blanks), Sentence Construction, Sentence Re-arrangements (Para Jumbles) (Narrative Sequencing), Comprehension / Reading Comprehension / Unseen Passages (Critical Reasoning) (Paragraph Questions), Cloze Test (Cloze Passage), Verbal Analogy (Word Based Analogy), Facts, Inference and Judgements
  6. Section 2 | Primary Maths & Reasoning: Ratio and Proportion (Ratios), Divisibility Rules, Mixture and Alligation, Permutation and Combination, Number System, HCF LCM, Sequence and Series (Series), Speed Time and Distance, Series (Number and Letter Series) (Numerical Relations and Reasoning), Coding Decoding, Non Verbal Reasoning (Spatial Aptitude) (Spatial Reasoning) (Visual Reasoning), Percentage, Average, Profit and Loss, Simple Interest and Compound Interest, Time and Work, Mensuration and Geometry, Age Problems, Arithmetic, Powers and Exponents (Surds and Indices), Algebra, Probability, Trigonometry, Syllogisms, Seating Arrangements, Blood Relations, Directions (Direction Test), Analytical Reasoning (Counting Figures Reasoning), Puzzle Solving (Puzzles), Calendar, Clock, Cubes & Dices, Venn Diagram, Data Arrangement, Inequality, Analogy, Ranking, Order and Sequence
  7. Section 2 | General Awareness (GK + Current Affairs): Polity, Physics, Biology, State Wise GK, Chemistry, History, Geography, Indian Economy, Environment, GK- Current Affairs, Static General Knowledge
  8. Section 3 | Computer System and Org. (CSO): Basics of COA, Floating Point Rep, Cache Memory Organization, Instr Formats & Modes, Programming the Basic Computer, Input Output Organisation, Register Transfer and Microoperations, Control Unit Design
  9. Section 3 | Database Management System: Basics of DBMS, ER Diagram, Relational Model & Functional Dependencies, Keys & Integrity Constraints, Normalization (1NF - BCNF), Decomposition Properties & 4NF, SQL, File Organization & Indexing, Relational Algebra, Relational Calculus, Transaction Management, Concurrency Control
  10. Section 3 | Operating System: Introduction to OS, Process Management, CPU Scheduling, Threads & Process Creation, Memory Management, Virtual Memory, Disc Scheduling, File Management, Process Synchronization
  11. Section 3 | Computer Networks: Introduction to CN, Data Communication, DLL: Access Control, DLL: Flow Control, DLL: Error Control, Data Link Layer - Ethernet, Net Layer: IPv4 & Proto, Net Layer: IP Addressing, Transport Layer Services, TL: Congestion & UDP, Application Layer, Hardware basics
  12. Section 3 | Data Structures: Introduction to DS, Array, Stack, Queue, Linked List, Tree, Graphs, Hashing, Algorithm Analysis, Time Complexity Analysis, Sorting Algorithms, Greedy Algorithms, Minimum Spanning Trees, Shortest Path Algos
  13. Section 3 | Theory Of Computation & Compiler Design: Introduction to TOC, Deterministic FA (DFA), Non-Deterministic FA, Regular Expressions, Grammar, Regular Language Properties, Moore & Mealy Machines, Pushdown Automata & CFG, Turing Machines, Intro to Compilers, Lexical Analysis, Grammar & CFG, Syntax Analysis: Top-Down, Syntax Analysis: Bottom-Up, Semantic Analysis & SDT, Intermediate Code Gen, Code Optimization
  14. Section 3 | Emerging Trends (AI, Societal Ethics & MS Office): Artificial Intelligence, Emerging Tech Trends, Society, Law & Ethics, MS Office Applications
  15. Section 3 | Software Engineering: Fundamentals of Software Engineering, Software Requirements and Quality Assurance, Software Design, Estimation and Metrics, Software Maintenance and Configuration Management, Software Testing
  16. Section 3 | C Programming: C Fundamentals, Control Flow, Functions, Arrays & Pointers, Storage Classes, Structures & Enums, DMA, Macros, Scoping & File Handling
  17. Section 3 | OOPS, C++, JAVA, HTML: OOPS with C++, Java, HTML Basics, CSS
  18. Section 3 | Java: Java Fundamentals, Array, String, IO & References
  19. Section 3 | Python: Introduction to Python, Tokens, Variables, Data Types, I/O, Operators & Expressions, Control Flow & Looping, Collections & Strings, Functions & Modules, File Handling & Data Analysis
  20. Section 3 | Digital Electronics: Digital Systems & Boolean Basics, Logic Gates & Hardware, Boolean Expression, Boolean Minimization, Combinational Circuit, Sequential Circuits, Number System, Number Representation
  21. Section 3 | Multimedia: Multimedia
  22. BPSC Previous Year Papers:
  23. BPSC Full Mock Tests:
AI summary & chapters

AI Summary

An AI-generated summary of this video lecture.

This lecture introduces computer memory hierarchy, focusing on primary volatile RAM and secondary non-volatile storage. It begins with a classification tree dividing memory into primary (RAM, ROM) and secondary categories, then defines RAM as the primary volatile memory that stores data currently in use. The instructor contrasts direct/random access with sequential access using hand-drawn diagrams and explains RAM's volatile nature, where data is lost when power is removed. The lesson then details SRAM as a 6-transistor flip-flop cell requiring no refreshing, making it fast but expensive and suited for CPU cache in processors like Intel Core i9 or AMD Ryzen. DRAM is presented as a 1-transistor, 1-capacitor cell that requires constant refreshing due to charge leakage but offers higher density for main system memory. A comparison table contrasts SRAM and DRAM across speed, density, cost, and structure. Finally, secondary memory is defined as non-volatile storage with examples including HDD, SD Card, PenDrive, and SSD. The memory hierarchy pyramid illustrates trade-offs between capacity, cost per unit storage, and access time across registers, cache, main memory, and disks.

Chapters

  1. 0:00 – 2:00 00:00-02:00

    The lecture opens with a memory classification tree showing primary and secondary branches, then presents an SRAM slide detailing its 6-transistor structure. A memory hierarchy pyramid illustrates trade-offs between capacity, cost, and access time across CPU, cache, main memory, and secondary storage. The instructor annotates the pyramid with red 'RAM' labels across register and main memory sections, then transitions to a slide defining RAM as the primary volatile memory that stores data currently in use. A hand-drawn diagram shows a row of memory cells indexed 0 to 4 with an 'X' value, illustrating direct access. On-screen text includes 'What is RAM (Random Access Memory)' and bullet points on Direct Access, Volatile Nature, Role in Processing, and Technology.

  2. 2:00 – 5:00 02:00-05:00

    The instructor defines RAM's volatile nature, noting it loses all stored information immediately when power is turned off. A red hand-drawn diagram contrasts sequential memory access with RAM's random/direct access capability. The memory hierarchy pyramid is annotated with red arrows showing the inverse relationship between capacity and access time, with labels for 'Capacity (More) / Per unit storage cost (Less) / Access Time (Less).' The lesson focuses on SRAM, whose slide states each memory cell uses a circuit of 6 Transistors (flip-flop) to store a single bit, requires No Refreshing as long as power is available, and serves as CPU Cache Memory in processors like Intel Core i9 or AMD Ryzen. The transition to DRAM describes its 1 Transistor and 1 Capacitor cell structure, with red circles highlighting the structural diagrams and underlines emphasizing 'refreshed' due to charge leakage requiring thousands of refreshes per second for Main System Memory.

  3. 5:00 – 6:32 05:00-06:32

    The lecture presents a comparison table titled 'COMPARISON BETWEEN SRAM AND DRAM,' with red arrows pointing to specific rows contrasting features like speed, density, cost, and structure. The DRAM slide reiterates the 1 Transistor and 1 Capacitor design and Refreshing Required characteristic. The lesson then transitions to 'What is Secondary Memory,' defining it as Non-Volatile memory with on-screen examples listing HDD, SD Card, PenDrive, and SSD. This concludes the primary memory discussion by distinguishing volatile RAM types from persistent secondary storage options.

The lecture follows a clear pedagogical progression: establishing the memory hierarchy framework, defining RAM's core properties (volatility and direct access), then differentiating its two main types. SRAM is characterized by a 6-transistor flip-flop cell, no refresh requirement, high speed, and use in CPU cache. DRAM is characterized by a 1-transistor-1-capacitor cell, mandatory refreshing due to capacitor charge leakage, higher density, and use as main system memory. The comparison table consolidates these distinctions across speed, density, cost, and structure. Secondary memory is introduced as non-volatile storage (HDD, SD Card, PenDrive, SSD), completing the primary-to-secondary memory classification. Key teaching tools include hand-drawn red annotations contrasting random versus sequential access, the hierarchy pyramid showing capacity-cost-access time trade-offs, and structural circuit diagrams for SRAM and DRAM cells. Real-world processor examples (Intel Core i9, AMD Ryzen) ground SRAM's cache application in practical context.

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