Practice Question (Gate 1990)

Duration: 2 min

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Module outline

  1. Discrete Mathematics: Permutation, Combination and Probability / क्रमचय, संचय एवं प्रायिकता, Set Theory, Relations, Functions, Propositional and Predicate Logic, Graph Theory, Group Theory
  2. Digital Logic: Digital Systems & Boolean Basics, Boolean Expression, Boolean Minimization, Logic Gates & Hardware, Combinational Circuit, Sequential Circuits, Number System, Number Representation, Floating Point Rep
  3. Computer Organization and Architecture: Basics of COA, Programming the Basic Computer, Cache Memory Organization, Input Output Organisation, Instr Formats & Modes, Register Transfer and Microoperations, Control Unit Design, Pipelining, Multiprocessors
  4. Programming: Language Design, C Fundamentals, Control Flow, Functions, Arrays & Pointers, Storage Classes, Structures & Enums, DMA, Macros, Scoping & File Handling, OOPS with C++
  5. Data Structures: Introduction to DS, Array, Linked List, Stack, Queue, Tree, Graphs, Hashing
  6. Algorithms: Algorithm Analysis, Time Complexity Analysis, Sorting Algorithms, Greedy Algorithms, Dynamic Programming, Minimum Spanning Trees, Shortest Path Algos, Advanced Algorithms
  7. Theory of Computation: Grammar, Regular Language Properties, Moore & Mealy Machines, Turing Machines
  8. Compiler Design: Intro to Compilers, Lexical Analysis, Grammar & CFG, Syntax Analysis: Top-Down, Syntax Analysis: Bottom-Up, Semantic Analysis & SDT, Intermediate Code Gen, Code Optimization, Run Time Environment, Introduction to TOC, Deterministic FA (DFA), Non-Deterministic FA, Regular Expressions, Pushdown Automata & CFG, Complexity Theory
  9. Operating Systems: Introduction to OS, Process Management, CPU Scheduling, Process Synchronization, Threads & Process Creation, Deadlock, Memory Management, Virtual Memory, Disc Scheduling, File Management, Unix OS, Linux OS, Security
  10. Database Management Systems: Basics of DBMS, ER Diagram, Relational Model & Functional Dependencies, Keys & Integrity Constraints, Normalization (1NF - BCNF), Decomposition Properties & 4NF, File Organization & Indexing, Relational Algebra, SQL, Relational Calculus, Transaction Management, Concurrency Control, ORDBMS, NoSQL
  11. Computer Networks: Introduction to CN, Data Communication, DLL: Access Control, DLL: Flow Control, DLL: Error Control, DLL: Framing, Data Link Layer - Ethernet, Net Layer: IPv4 & Proto, Net Layer: IP Addressing, Net Layer:Routing Protocol, Transport Layer Services, TL: Congestion & UDP, Application Layer, Hardware basics, Network Security
AI summary & chapters

AI Summary

An AI-generated summary of this video lecture.

The video presents an educational lecture on computer architecture, specifically solving a cache memory addressing problem from a 1990 Gate exam. The instructor analyzes a block-set associative cache system with 128 blocks divided into four sets, a main memory of 16,384 blocks, and a block size of 256 eight-bit words. The lecture addresses two key questions: determining the total bits required for main memory addressing and calculating the bit distribution for the Tag, Set, and Word fields. The instructor uses a diagram to visually break down the physical address into its constituent parts.

Chapters

  1. 0:00 – 1:47 00:00-01:47

    The video opens with a static slide displaying a computer architecture problem. The text reads: 'A block-set associative cache memory consists of 128 blocks divided into four block sets. The main memory consists of 16,384 blocks and each block contains 256 eight-bit words.' The instructor reads these parameters aloud, highlighting the cache size, set count, main memory capacity, and block size. He identifies the two questions to be answered: total address bits and field breakdown.

The lecture demonstrates a step-by-step approach to solving cache addressing problems. It starts with parsing the problem parameters, then calculates the physical address width, and finally decomposes this address into the specific fields required for cache lookup (Tag, Set, Offset). The visual aid of the diagram helps in understanding how the address bits are partitioned between the main memory and the cache components.

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